1. Field of the Invention
The present invention generally relates to the plasma processing of a substrate. More particularly, the present invention relates to an improved method for etching vias in the backside of a gallium arsenide substrate within a plasma processing chamber.
2. Description of the Background Art
GaAs devices are used extensively in the wireless telecommunications industry, where the high electron mobility of GaAs makes it well suited for high frequency, low noise, high gain applications. Although it has excellent electrical properties, GaAs is a relatively poor thermal conductor, making it difficult to remove heat efficiently from power devices. A commonly used solution to this issue is the formation of vias from the wafer backside to the frontside circuitry. Such vias provide a good thermal path for heat removal as well as a low impedance ground connection for RF (radio frequency) devices.
After completion of the frontside processing, the wafer is mounted face down on a carrier wafer and mechanically thinned to a thickness of approximately 100 microns. The back of the wafer is then patterned using photo-resist and the vias are plasma etched through the thinned substrate, stopping on the frontside metal. After resist removal the vias are metallized, typically by sputtering a gold seed layer followed by a gold plating step, to act as the heat sink/ground connection.
Ideally the backside etch process results in a via that has smooth sloped walls. However, in practice, pillar (also known as grass) formation often occurs in a number of vias. FIG. 1 shows typical pillar formations 2. These pillar formations 2 are potentially harmful to reliable metallization of the via 4 etch in the substrate 6. Pillar formations potentially arise from a number of sources. For example, contamination on the etched surface such as residuals from the thinning process or impurities in the substrate either prior to, or exposed during, the etch may act as a micromask. In addition, this micromask effect can also result from introduction of H2O during sample loading, sputtering and redeposition of nonvolatile mask materials, sputtering and redeposition from reactor components, and formation of low volatility etch products (GaCl2 vs. GaCl3).
Nam et al. addressed pillar formations in a recent journal article. This group concluded that pillar formation depends on the surface condition of the wafer after the grinding process. In addition, the group discovered that pillars form more easily when the physical conditions set forth below are satisfied.
Lower bias powers<100WLower ICP powers<700WHigher pressure>13mtorrLower BCl3 compositions<66%BCl3
Based upon their observations, the Nam et al. group recommended the following process conditions.
BCl340sccmCl220sccmPressure8mtorrRF Bias Power50WICP Power700W
In addition, the Nam et al. group recommended an Ar sputter pre-etch to physically remove any residuals from the grind process. Nevertheless, experimentation by the present inventors has shown that pillar formations may occur even when there is compliance with the suggested process conditions. Additionally, the process conditions suggested by Nam et al. result in a relatively low etch rate for the GaAs (<3 micron/minute) which results in a process time of >30 minutes for a typical 100 micron deep via. This problem is expected to be more severe for 150 mm substrates, compared to the 3 inch substrates used by Nam et al.
In view of the above discussed problems with the prior art, what is needed is a high rate, GaAs via etch process that results in sloped via profiles and eliminates pillar formation. Furthermore, the operating parameters for the process should be specified such that the process can be implemented as a production worthy process.